High speed bipolar D latches, such as ECL master-slave flip-flop circuits of the type used in integrated circuit memory devices, transfer binary information existing at the inputs of the master portion to the slave portion thereof in response to a predetermined transitions of a clock signal. This data is stored in and provided at the output terminals of the flip-flop by the slave portion until the next predetermined transition of the clock signal, at which time the data then being supplied to the input terminals of the master portion is stored in the slave portion of the circuit.
High speed bipolar current switches have an undesirable performance characteristic in that the differential output voltage of the latch is reduced upon latch clock transitions which can cause problems with downstream circuitry.
FIG. 1 illustrates a typical high speed bipolar D latch. Q1 and Q2 make up the clocking portion of the latch. Q5 and Q6 make up the memory cell portion of the latch. Q3 and Q4 make up the data input portion of the latch. Clocking of the latch determines which pair of transistors controls the outputs; Q3/Q4 with clock high; Q5/Q6 with clock low. As shown in FIG. 1A, on clock transitions there is an undesirable momentary reduction of latch output voltage as Q3/Q4 and Q5/Q6 turn on and off as the current path from I1 switches between the transistor pairs.
FIG. 2 illustrates a variation of the D latch of FIG. 1 which partially solves the problems associated with clock edge transitions. The memory cell portion of the latch is constantly biased and as a result the output voltages to the first order are not affected by clock transitions. One disadvantage of this circuit is the use of clamp diodes D1 and D2 which slow the operation of the latch. Another disadvantage is that the output voltage swing will vary depending on the clock phase since the clock and data portions of the latch are tied directly to the output.